Checking Designs

Verifying a design can be a complex task. An automatic design rule check is the standard for many years in the area of IC design and it is getting more and more standard in the area of MEMS, Microwave,PCBs, etc. A versatile Design Rule Checker is integrated into the LayoutEditor. A complete design check can be triggered by calling a DRC macro. Also any single check can be called manually. The LayoutEditor supports many different design rule checks. More checks are supported than a simple IC design requires. For all tests the area to be checked can be specified as well as the way rule violations are reported. As a matter of course, all design rule checks work on all angle elements. Design rule checks are not intended to check Multi-Gigabit designs, it will leak on performance but will work if you have a powerful system and enough run time to operate. Designs with up to over some million shapes are no problem, even if computationally intensive options are used.

Illustration

DRC violations can is reported in three ways:

Graphical Illustration

The shape violating the rule will be displayed in the main drawing on a own error layer. The basic concept behind a graphic violation display is: A new cell will be created named as the checked cell having a suffix with the name of the design rule check. All detected errors are added to this cell on an error layer. A new cell reference to this cell is added to the unmodified original cell. If an identical check was performed before, the earlier results are deleted. Use ClearDRC to delete any prior results. If this method should be used, the error layer and the feature to delete detected violations are setup in the DRC dock window. The DRC dock windows will be opened by calling any DRC feature from the Utilities menu.

Design-check-example

Listing Violations

A list will be generated showing each detected violation, with one violation per line. Each line contains a symbol, the name of the check and, where applicable, the measured value. By clicking on the list, the current view is directed to the location of the violation. A double click will mark the entry. The violation list can be stored and loaded. The violation list can be be deleted manually or by a macro.

violation-list

Summarizing Report

Next to the graphical display and the violation list a summarizing report can be created. It contains a list of all checkes being made with the amount of violations.

Check Area

The area being checked can be defined. It can be checked the whole cell, a user-defined region or the shapes in the current view. If the check region is limited, all applicable violations in the check area will be found. Depending on the type of check, some violations near the border region also may be displayed.

Entering the Check Rules

All Design Rule Check can be enter within the graphical user interface. Each check will have a own user interface to enter the required check values.

DRC Macro

Each DRC check available in the user interface performs only a single check. A complete DRC usually requires many individual rules. For a complete DRC in a single step, a macro must be created with all the necessary rules folded into it. When doing so, each rule can be given an individual name. This macro shown below provides an example. It represents a part of the sample macros shipped with LayoutEditor.

#!/usr/bin/layout
#name=Macro: drc example.layout
#help=example for a drc macro

int main(){

layout->drcTool->result="DRC (LayoutEditor example) \r\n";

// setup error layer
layout->drawing->activeLayer=0;
layout->drcTool->setErrorLayerToActiveLayer();

// check for layer metal 1
layout->drcTool->ruleName= "Minimum Size Metal1";
layout->drcTool->minimumSize(800,6,true);
layout->drcTool->ruleName= "Minimum Distance Metal1";
layout->drcTool->minimumElementDistance(800,6,true);

// check for layer metal 2
layout->drcTool->ruleName= "Minimum Size Metal2";
layout->drcTool->minimumSize(900,8,true);
layout->drcTool->ruleName= "Minimum Distance Metal2";
layout->drcTool->minimumElementDistance(900,8,true);

// check for via1  (metal1 to metal2)
layout->drcTool->ruleName= "Via in metal1";
layout->drcTool->inside(50,7,6);
layout->drcTool->ruleName= "Via in metal2";
layout->drcTool->inside(60,7,8);

layout->drcTool->showReport();

}