A Spectra Design File (extension .dsn) is the input to a Specctra-style PCB autorouter. It describes the board: layers, outline, keepouts, component footprints, pin locations, nets, design rules, and any copper that is already there. The matching output of that router is a SES (Spectra Session File). Together they form the classic Cadence Specctra / Electra exchange: the layout tool writes DSN, the router reads DSN and writes SES, and the layout tool reads SES back.
The format is an ASCII S-expression language (Lisp-style parentheses), the same family as SES. It is widely used by PCB routers such as Cadence Specctra, Electra, and FreeRouting. It is not an IC mask format (unlike GDSII) and it is not LEF/DEF, which are the digital-IC pair used with OpenROAD.
LayoutEditor writes DSN from Save and from Auto-Router, and does not read it. Opening, importing or updating a .dsn file reports that load is not supported. Bring routing results back with SES.
Typical use is: prepare the current cell with a netlist that is not an extracted netlist, placed components (cell references with a device name), and conductor and via layers in the layer setup. Pin names on devices are text on conductor layers. Export the cell as DSN, or run Auto-Router, which writes DSN for you. The router — for example FreeRouting, shipped with the LayoutEditor — reads the .dsn and writes a .ses. Import that SES to add wires and vias.
LayoutEditor --DSN--> autorouter --SES--> LayoutEditor
(geometry, (places & (wires, vias,
nets, pads) routes) placements)Save with type Spectra Design File writes the current cell plus the current netlist to a .dsn file. The file dialog lists that type as Spectra Design File (.dsn). Open, Import and Update are not supported; the reader reports that load of DSN files is not supported. Saving as SES is not a DSN operation either: SES cannot be written. The exchange is always DSN out and SES in.
Export fails if there is no layout window, no netlist tool, no current netlist, or the current netlist is of type extracted. The writer first rebuilds connectivity and extracts a netlist of the current cell so existing copper can be mapped onto schematic nets.
Under Place & Route, Autoroute can call an external tool. A typical setup uses input format dsn, output format ses, and the FreeRouting executable included in the LayoutEditor package. The editor writes a .dsn named after the cell in a temporary folder, runs the tool, then imports the matching .ses into the current cell. Hold Shift and press Auto-Router to change that setup. DEF in and out is the other pair (for example OpenROAD). The internal native router, available when compiled in with the use_router qmake option, does not use DSN or SES.
Before export there must be a netlist selected in the netlist tool (schematic or placed), with devices that match cell-reference device names. Conductor layers (type conductor) and via layers are required; layer names become DSN layer and padstack names. In each device cell, a text on a conductor layer is a pin: the text string is the pin name, and other shapes on the same electrical node become the padstack. An optional board outline can be drawn on the layer given by dsnBoundaryLayer in the Setup dialog (default layer 5). Optional keepout shapes go on the layers listed in dsnKeepoutLayer (default the string 4, comma-separated layer numbers). Those keepouts apply to all signal layers. Both settings are also members of the setup class.
A DSN file is UTF-8 or ASCII text. Parentheses group a scope; the first token after the opening parenthesis is the keyword. Tokens are separated by space, tab, or newline. Names that contain a space, minus, plus, parenthesis, or slash are written in double quotes. Coordinates and widths are decimal numbers in micrometres (see Units).
The LayoutEditor writer emits one top-level pcb scope and the children listed in the reference. Specctra allows further keywords such as session, floor_plan, and extra wire styles; those are not written here.
Export always writes resolution um 1 and unit um. Database units are converted so that one DSN unit is one micrometre. Origin and axis match the current cell. Rotation in a place record is in degrees.
The SES importer assumes the same micrometre scale. Do not change the resolution line in a file you intend to round-trip through the LayoutEditor.
The LayoutEditor writes a pcb scope whose name is the path passed to Save (often a full path). Inside it come parser, resolution, unit, structure, placement, library, network, and wiring, in that order.
The parser scope tells the router that quoted strings use a double-quote character and that spaces inside quotes are part of the name. It also records host_cad as LayoutEditor and host_version as the LayoutEditor release string.
resolution um 1 together with unit um means one DSN unit is one micrometre. The 1 is a scale factor: coordinates are already in micrometres, not in hundredths of a micrometre.
The structure scope holds the board stack, outline, keepouts, allowed vias, and default rules. Each LayoutEditor conductor layer becomes one signal layer, exported from highest level to lowest (typical PCB: top first). Index 0 is the first exported conductor. The layer name is the LayoutEditor layer name, quoted if it contains spaces or the characters minus, plus, or parentheses. Power or plane layers are not emitted as type power; every exported conductor is signal.
There is always one boundary rectangle of the cell bounding box, with layer name pcb. Additionally, every path, polygon or box on the dsnBoundaryLayer is written as another boundary shape of type signal. Use that for a non-rectangular board outline.
Keepouts are shapes the router must not cross. A path, polygon or box on a layer listed in dsnKeepoutLayer becomes a keepout of type signal (all signal layers). A path, polygon or box on a conductor layer that is not assigned to a net becomes a keepout on that copper layer. Existing copper that does belong to a net is not a keepout; it is written under wiring as protected wire.
The via list names the padstacks the router may use, for example via_Via1_layout and via_global_via_layout. Those names match the library padstacks: via_ plus the via layer name plus _layout for each via layer except the global via, and via_global_via_layout if a global via layer is set.
The rule inside structure is the default trace width and clearance for the whole board: the maximum conductor type-parameter 1 (width) and type-parameter 2 (clearance) among all conductor layers, converted to micrometres. Per-layer values are repeated under network, class, and layer_rule.
placement groups components by footprint cell. Each place record has the instance device name, X and Y of the cell-reference origin in micrometres, side front or back from the cell frontOfPCB flag, and the strans angle in degrees. If the instance is mirrored in X, the angle is negated and a mirror X flag is written. A place record that contains only the device name means the netlist device is not placed yet. Only cell references whose device name exists in the current netlist are exported as placed.
The library holds footprints (image) and copper stacks (padstack). There is one image per used footprint cell. Each pin is a text on a conductor layer in the device cell: the pin name is the text string, the position is the text origin relative to the cell origin, and the padstack name is pad0, pad1, and so on. A conductor shape with type protect is a path, polygon or box on a conductor layer whose node is not a pin node — fixed copper inside the footprint. If the device cell is mounted on the back, the writer copies the cell, flips PCB front and back, rotates 180°, then extracts pins so pin coordinates match the Specctra back-side convention.
Pin padstacks (pad0, pad1, …) collect all non-text shapes on the same node as the pin text, on conductor layers, coordinates relative to the pin. Identical shape lists share one padstack. If a pin has no copper, a dummy circle of 0.01 micrometres (10 nm) is used. All pin padstacks have attach off.
Via padstack via_global_via_layout is an enclosure on every conductor layer. The diameter is via type-parameter 1 plus twice parameter 2. The shape is a circle if parameter 5 is 2, otherwise a centred rectangle. Padstack via_ plus the via layer name plus _layout is an enclosure on the conductor below (level minus one, parameter 3) and above (level plus one, parameter 2) that via layer, with the same circle-or-rectangle rule. These names must stay unchanged if you expect SES import to rebuild vias.
The network has one net scope per netlist node. Pins are written as device name, hyphen, pin name, using the same names as placement and image. All nets are put in one class named LayoutEditor_default. That class repeats the board-wide width and clearance, then a layer_rule per conductor (type-parameter 1 is width, type-parameter 2 is clearance), and a circuit use_via list that matches the structure via list.
wiring is existing copper on the top cell that belongs to a net, marked so the router keeps it. A path, polygon or box on a conductor layer mapped to a schematic net becomes a wire of type protect. A path, polygon or box on a via or global via layer mapped to a net becomes a via of type protect at the shape centre, using the matching padstack. Unmapped copper is not wired; it was already exported as keepout. type protect is why the SES importer skips those objects when the router echoes them back.
Shapes used in boundary, keepout, image, padstack and wire follow a small mapping. A box becomes a rect with layer and two corners. A polygon that is a circle becomes a circle with layer, diameter, and optional centre. Any other polygon becomes a polygon with layer, unused path width 0, and the vertex list. A path becomes a path with layer, width and vertices; if the cap is not round, apertur_type square is added. The layer name is omitted only when the surrounding scope already implies it; the writer usually includes it.
Two pads, one net, two signal layers, in micrometres. This is the kind of file Auto-Router and FreeRouting consume:
(pcb example.dsn
(parser
(string_quote ")
(space_in_quoted_tokens on)
(host_cad "LayoutEditor")
(host_version "20260828")
)
(resolution um 1
)
(unit um
)
(structure
(layer top
(type signal)
(property
(index 0)
)
)
(layer bottom
(type signal)
(property
(index 1)
)
)
(boundary
(rect pcb 0.000000 0.000000 4000.000000 3000.000000)
)
(via via_Via1_layout)
(rule
(width 100.000000)
(clearance 100.000000)
)
)
(placement
(component PAD
(place A 800.000000 1500.000000 front 0)
(place B 3200.000000 1500.000000 front 0)
)
)
(library
(image PAD
(pin pad0 pin1 0.000000 0.000000)
)
(padstack pad0
(shape (rect top -200.000000 -200.000000 200.000000 200.000000))
(attach off)
)
(padstack via_Via1_layout
(shape (circle top 400.000000))
(shape (circle bottom 400.000000))
(attach off)
)
)
(network
(net N1
(pins A-pin1 B-pin1)
)
(class LayoutEditor_default "" N1
(rule
(width 100.000000)
(clearance 100.000000)
)
(layer_rule top
(rule
(width 100.000000)
(clearance 100.000000)
)
)
(layer_rule bottom
(rule
(width 100.000000)
(clearance 100.000000)
)
)
(circuit
(use_via via_Via1_layout)
)
)
)
(wiring
)
)After routing, import the SES that belongs to this design.
Reading DSN always fails (Open, Import, Update). Export requires a schematic or placed netlist, not an extracted one, and skips cell references without a device name and devices that are not in the netlist. Only conductor layers become signal layers. Power-plane DSN layer types, net classes other than LayoutEditor_default, from-tos, and extra Specctra rules such as clearance_class or via_at_smd are not written. Changing the resolution line and expecting SES import to follow it will scale the result wrongly.
Cadence Specctra manuals describe additional design-file keywords. Routers generally ignore unknown scopes; the LayoutEditor only writes the subset above.